392 lines
11 KiB
C++
392 lines
11 KiB
C++
/*
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Enc28J60NetworkClass.cpp — Bitbang-SPI version for non-hardware-SPI pins
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Based on UIPEthernet by Norbert Truchsess, GPL V2
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Modification: Hardware SPI replaced with bitbang SPI.
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Target: STM32F103RBT6 with ENC28J60 on PC6(SCK)/PC7(MISO)/PC8(CS)/PC9(MOSI)
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*/
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#include "Enc28J60Network.h"
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#include <Arduino.h>
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#include "config.h" // ETH_SCK_PIN / ETH_MOSI_PIN / ETH_MISO_PIN
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// Note: <SPI.h> intentionally NOT included — this version uses bitbang SPI
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extern "C" {
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#include "enc28j60.h"
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#include "uip.h"
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}
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// ============================================================
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// Bitbang SPI — SPI Mode 0 (CPOL=0, CPHA=0)
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// Pin definitions come from project include/config.h via build system
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// ============================================================
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#ifndef ETH_SCK_PIN
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#error "ETH_SCK_PIN not defined — check include/config.h"
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#endif
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static bool _spi_ready = false;
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static void bitbang_init() {
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if (_spi_ready) return;
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pinMode(ETH_SCK_PIN, OUTPUT); digitalWrite(ETH_SCK_PIN, LOW);
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pinMode(ETH_MOSI_PIN, OUTPUT); digitalWrite(ETH_MOSI_PIN, LOW);
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pinMode(ETH_MISO_PIN, INPUT);
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_spi_ready = true;
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}
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static inline uint8_t bitbang_transfer(uint8_t out) {
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uint8_t in = 0;
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for (int8_t i = 7; i >= 0; i--) {
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digitalWrite(ETH_MOSI_PIN, (out >> i) & 1);
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digitalWrite(ETH_SCK_PIN, HIGH);
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in = (in << 1) | digitalRead(ETH_MISO_PIN);
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digitalWrite(ETH_SCK_PIN, LOW);
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}
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return in;
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}
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// ============================================================
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// set CS to 0 = active
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#define CSACTIVE digitalWrite(csPin, LOW)
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// set CS to 1 = passive
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#define CSPASSIVE digitalWrite(csPin, HIGH)
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bool Enc28J60Network::spiInitialized = false;
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uint8_t Enc28J60Network::csPin = SS;
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uint16_t Enc28J60Network::nextPacketPtr;
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uint8_t Enc28J60Network::bank = 0xff;
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struct memblock Enc28J60Network::receivePkt;
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void Enc28J60Network::initSPI()
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{
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if (spiInitialized)
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return;
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bitbang_init();
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pinMode(csPin, OUTPUT);
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CSPASSIVE;
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spiInitialized = true;
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}
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bool Enc28J60Network::init(uint8_t* macaddr)
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{
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MemoryPool::init();
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initSPI();
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// perform system reset
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writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
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delay(50);
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nextPacketPtr = RXSTART_INIT;
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writeRegPair(ERXSTL, RXSTART_INIT);
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writeRegPair(ERXRDPTL, RXSTART_INIT);
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writeRegPair(ERXNDL, RXSTOP_INIT);
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writeReg(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN);
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writeRegPair(EPMM0, 0x303f);
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writeRegPair(EPMCSL, 0xf7f9);
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writeRegPair(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
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writeOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
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writeRegPair(MAIPGL, 0x0C12);
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writeReg(MABBIPG, 0x12);
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writeRegPair(MAMXFLL, MAX_FRAMELEN);
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writeReg(MAADR5, macaddr[0]);
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writeReg(MAADR4, macaddr[1]);
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writeReg(MAADR3, macaddr[2]);
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writeReg(MAADR2, macaddr[3]);
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writeReg(MAADR1, macaddr[4]);
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writeReg(MAADR0, macaddr[5]);
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phyWrite(PHCON2, PHCON2_HDLDIS);
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setBank(ECON1);
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writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
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phyWrite(PHLCON, 0x476);
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return getrev();
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}
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memhandle Enc28J60Network::receivePacket()
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{
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uint8_t rxstat;
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uint16_t len;
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if (readReg(EPKTCNT) != 0)
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{
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uint16_t readPtr = nextPacketPtr+6 > RXSTOP_INIT ?
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nextPacketPtr+6-((RXSTOP_INIT + 1)-RXSTART_INIT) : nextPacketPtr+6;
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writeRegPair(ERDPTL, nextPacketPtr);
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nextPacketPtr = readOp(ENC28J60_READ_BUF_MEM, 0);
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nextPacketPtr |= readOp(ENC28J60_READ_BUF_MEM, 0) << 8;
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len = readOp(ENC28J60_READ_BUF_MEM, 0);
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len |= readOp(ENC28J60_READ_BUF_MEM, 0) << 8;
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len -= 4;
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rxstat = readOp(ENC28J60_READ_BUF_MEM, 0);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
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if ((rxstat & 0x80) != 0)
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{
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receivePkt.begin = readPtr;
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receivePkt.size = len;
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return UIP_RECEIVEBUFFERHANDLE;
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}
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setERXRDPT();
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}
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return (NOBLOCK);
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}
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void Enc28J60Network::setERXRDPT()
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{
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writeRegPair(ERXRDPTL, nextPacketPtr == RXSTART_INIT ? RXSTOP_INIT : nextPacketPtr-1);
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}
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memaddress Enc28J60Network::blockSize(memhandle handle)
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{
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return handle == NOBLOCK ? 0 :
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handle == UIP_RECEIVEBUFFERHANDLE ? receivePkt.size : blocks[handle].size;
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}
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bool Enc28J60Network::sendPacket(memhandle handle)
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{
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memblock *packet = &blocks[handle];
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uint16_t start = packet->begin;
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uint16_t end = start + packet->size - 1 - UIP_SENDBUFFER_PADDING;
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writeByte(start, 0);
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writeRegPair(ETXSTL, start);
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writeRegPair(ETXNDL, end);
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bool success = false;
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for (uint8_t retry = 0; retry < TX_COLLISION_RETRY_COUNT; retry++)
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{
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
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writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
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writeOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXERIF | EIR_TXIF);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
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uint8_t eir;
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while (((eir = readReg(EIR)) & (EIR_TXIF | EIR_TXERIF)) == 0);
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writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
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success = ((eir & EIR_TXERIF) == 0);
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if (success) break;
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uint8_t tsv4 = readByte(end + 4);
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if (!(tsv4 & 0b00100000)) break;
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}
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return success;
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}
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uint16_t Enc28J60Network::setReadPtr(memhandle handle, memaddress position, uint16_t len)
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{
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memblock *packet = handle == UIP_RECEIVEBUFFERHANDLE ? &receivePkt : &blocks[handle];
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memaddress start = handle == UIP_RECEIVEBUFFERHANDLE &&
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packet->begin + position > RXSTOP_INIT ?
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packet->begin + position-((RXSTOP_INIT + 1)-RXSTART_INIT) :
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packet->begin + position;
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writeRegPair(ERDPTL, start);
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if (len > packet->size - position) len = packet->size - position;
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return len;
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}
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uint16_t Enc28J60Network::readPacket(memhandle handle, memaddress position, uint8_t* buffer, uint16_t len)
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{
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len = setReadPtr(handle, position, len);
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readBuffer(len, buffer);
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return len;
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}
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uint16_t Enc28J60Network::writePacket(memhandle handle, memaddress position, uint8_t* buffer, uint16_t len)
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{
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memblock *packet = &blocks[handle];
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uint16_t start = packet->begin + position;
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if (len > packet->size - position) len = packet->size - position;
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if (len == 0) return 0;
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writeRegPair(EWRPTL, start);
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writeBuffer(len, buffer);
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return len;
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}
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uint8_t Enc28J60Network::readByte(uint16_t addr)
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{
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writeRegPair(ERDPTL, addr);
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CSACTIVE;
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bitbang_transfer(ENC28J60_READ_BUF_MEM);
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uint8_t c = bitbang_transfer(0x00);
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CSPASSIVE;
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return c;
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}
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void Enc28J60Network::writeByte(uint16_t addr, uint8_t data)
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{
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writeRegPair(EWRPTL, addr);
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CSACTIVE;
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bitbang_transfer(ENC28J60_WRITE_BUF_MEM);
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bitbang_transfer(data);
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CSPASSIVE;
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}
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void Enc28J60Network::copyPacket(memhandle dest_pkt, memaddress dest_pos, memhandle src_pkt, memaddress src_pos, uint16_t len)
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{
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memblock *dest = &blocks[dest_pkt];
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memblock *src = src_pkt == UIP_RECEIVEBUFFERHANDLE ? &receivePkt : &blocks[src_pkt];
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memaddress start = src_pkt == UIP_RECEIVEBUFFERHANDLE && src->begin + src_pos > RXSTOP_INIT ?
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src->begin + src_pos - ((RXSTOP_INIT + 1) - RXSTART_INIT) : src->begin + src_pos;
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enc28J60_mempool_block_move_callback(dest->begin + dest_pos, start, len);
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}
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void enc28J60_mempool_block_move_callback(memaddress dest, memaddress src, memaddress len)
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{
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if (len == 1)
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{
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Enc28J60Network::writeByte(dest, Enc28J60Network::readByte(src));
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}
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else
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{
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len += src - 1;
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Enc28J60Network::writeRegPair(EDMASTL, src);
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Enc28J60Network::writeRegPair(EDMADSTL, dest);
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if ((src <= RXSTOP_INIT) && (len > RXSTOP_INIT))
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len -= ((RXSTOP_INIT + 1)-RXSTART_INIT);
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Enc28J60Network::writeRegPair(EDMANDL, len);
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Enc28J60Network::writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_CSUMEN);
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Enc28J60Network::writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_DMAST);
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while (Enc28J60Network::readOp(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_DMAST);
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}
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}
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void Enc28J60Network::freePacket()
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{
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setERXRDPT();
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}
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uint8_t Enc28J60Network::readOp(uint8_t op, uint8_t address)
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{
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CSACTIVE;
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bitbang_transfer(op | (address & ADDR_MASK));
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if (address & 0x80) bitbang_transfer(0x00); // dummy read for MAC/MII
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uint8_t c = bitbang_transfer(0x00);
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CSPASSIVE;
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return c;
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}
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void Enc28J60Network::writeOp(uint8_t op, uint8_t address, uint8_t data)
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{
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CSACTIVE;
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bitbang_transfer(op | (address & ADDR_MASK));
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bitbang_transfer(data);
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CSPASSIVE;
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}
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void Enc28J60Network::readBuffer(uint16_t len, uint8_t* data)
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{
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CSACTIVE;
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bitbang_transfer(ENC28J60_READ_BUF_MEM);
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while (len--) *data++ = bitbang_transfer(0x00);
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CSPASSIVE;
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}
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void Enc28J60Network::writeBuffer(uint16_t len, uint8_t* data)
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{
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CSACTIVE;
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bitbang_transfer(ENC28J60_WRITE_BUF_MEM);
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while (len--) bitbang_transfer(*data++);
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CSPASSIVE;
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}
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void Enc28J60Network::setBank(uint8_t address)
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{
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if ((address & BANK_MASK) != bank)
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{
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writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5);
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bank = (address & BANK_MASK);
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}
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}
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uint8_t Enc28J60Network::readReg(uint8_t address)
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{
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setBank(address);
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return readOp(ENC28J60_READ_CTRL_REG, address);
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}
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void Enc28J60Network::writeReg(uint8_t address, uint8_t data)
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{
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setBank(address);
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writeOp(ENC28J60_WRITE_CTRL_REG, address, data);
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}
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void Enc28J60Network::writeRegPair(uint8_t address, uint16_t data)
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{
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setBank(address);
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writeOp(ENC28J60_WRITE_CTRL_REG, address, (data & 0xFF));
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writeOp(ENC28J60_WRITE_CTRL_REG, address+1, (data >> 8));
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}
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void Enc28J60Network::phyWrite(uint8_t address, uint16_t data)
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{
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writeReg(MIREGADR, address);
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writeRegPair(MIWRL, data);
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while (readReg(MISTAT) & MISTAT_BUSY) delayMicroseconds(15);
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}
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uint16_t Enc28J60Network::phyRead(uint8_t address)
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{
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writeReg(MIREGADR, address);
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writeReg(MICMD, MICMD_MIIRD);
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while (readReg(MISTAT) & MISTAT_BUSY) delayMicroseconds(15);
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writeReg(MICMD, 0);
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return (readReg(MIRDL) | readReg(MIRDH) << 8);
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}
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void Enc28J60Network::clkout(uint8_t clk)
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{
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writeReg(ECOCON, clk & 0x7);
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}
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uint8_t Enc28J60Network::getrev(void)
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{
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initSPI();
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return readReg(EREVID);
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}
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uint16_t Enc28J60Network::chksum(uint16_t sum, memhandle handle, memaddress pos, uint16_t len)
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{
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uint16_t t;
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len = setReadPtr(handle, pos, len) - 1;
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CSACTIVE;
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bitbang_transfer(ENC28J60_READ_BUF_MEM);
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uint16_t i;
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for (i = 0; i < len; i += 2)
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{
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t = bitbang_transfer(0x00) << 8;
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t += bitbang_transfer(0x00);
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sum += t;
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if (sum < t) sum++;
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}
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if (i == len)
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{
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t = (bitbang_transfer(0x00) << 8) + 0;
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sum += t;
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if (sum < t) sum++;
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}
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CSPASSIVE;
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return sum;
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}
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void Enc28J60Network::powerOff()
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{
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writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
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delay(50);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_VRPS);
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delay(50);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PWRSV);
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}
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void Enc28J60Network::powerOn()
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{
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writeOp(ENC28J60_BIT_FIELD_CLR, ECON2, ECON2_PWRSV);
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delay(50);
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writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
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delay(50);
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}
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bool Enc28J60Network::linkStatus()
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{
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return (phyRead(PHSTAT2) & 0x0400) > 0;
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}
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